1. Field of the Invention
The present invention concerns integrated circuits (ICs) and IC design, and particularly relates to the assignment of specific metal layers to electrical connection (or wire) segments during integrated circuit design.
2. Description of the Related Art
FIG. 1 provides a simplified cross-sectional view of an integrated circuit chip (or die) 50, which includes a semiconductor layer 60, four metal layers 51 to 54, electrically insulating layers 57, and passivation layer 58. Semiconductor layer 60, which is typically polysilicon, is used for forming the transistors and other electronic devices and also may be used for routing some of the electrical connections between these electronic devices. However, wire routing occupies space on the semiconductor layer 60 which otherwise could be used for the electronic devices. As a result, ordinarily only the shorter electrical connections are formed on semiconductor layer 60. For the remainder of the connections, metal layers 51 to 54 are provided.
Metal layers 51 to 54 may be formed from any of a variety of materials including aluminum, copper or an electrically conductive alloy. To simplify the routing process, routing typically is performed using mainly horizontal and vertical electrical connection (or wire) segments. Moreover, to permit such routing to be performed in an orderly manner, each metal layer typically is designated as either a horizontal metal layer or a vertical metal layer. Horizontal metal layers are used primarily for horizontal wire segments and vertical metal layers are used primarily for vertical wire segments. Thus, integrated circuit chip 50 typically will have two of its metal layers designated as vertical layers (e.g., layers 51 and 53 ) and two of its metal layers designated as horizontal layers (e.g., layers 52 and 54 ). Ordinarily, horizontal and vertical metal layers are alternated so as to facilitate horizontal-to-vertical transitions. It is also common to number the metal layers in ascending order starting with the metal layer closest to the semiconductor layer. Thus, metal layers 51 to 54 would be referred to as M1 to M4, respectively. This designation is used herein.
Between each pair of adjacent metal layers and between metal layer 51 and semiconductor layer 60 is an electrically insulating layer 57, which typically is formed as an oxide film. Electrical connections between metal layers are made using interlayer holes called vias, while direct contacts can be made between semiconductor layer 60 and metal layer 51.
Passivation layer 58 functions to prevent the deterioration of the electrical properties of the die caused by water, ions and other external contaminants. Typically, passivation layer 58 is made of a scratch-resistant material such as silicon nitride and/or silicon dioxide.
As indicated above, current integrated circuits frequently include four metal layers. Moreover, the number of metal layers utilized has been increasing over the past few years, and it is expected that this trend will continue. However, in order to utilize such multiple metal layers, it is necessary to assign each wire segment to a specific metal layer. Unfortunately, until now, no systematic and efficient technique for assigning wire segments to specific metal layers has been proposed.